Business Wire

Complete Chip Fabrication Processes and Cost Estimation of Murata SAW Thermo-Compensated Band 8 Filter In Low Band Front-End Module - Research and Markets

DUBLIN--(BUSINESS WIRE)--Research and Markets has announced the addition of the "Murata SAW Thermo-Compensated Band 8 Filter In Low Band Front-End Module" report to their offering. In Front-End Filter ...
Design-Reuse

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...
Electronics Weekly

LETI integrates III-V lasers on 200mm wafers using CMOS flow

Leti has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This shows the way to transitioning away from 100mm wafers and a process based on bulk III-V ...
EDN

2-Mpixel CMOS sensor module

Boise, Idaho — The MT9D111 is a 2-Mpixel CMOS senor module optimized for cellular phone designs. This module includes a microcontroller, 10-bit ADC, advanced color interpolation or truer color ...
Electronic Design

CMOS Plus On-Chip Electro-Optical Interconnect Zooms Past 2 Tb/s

DARPA, Intel, and Ayar Labs collaborate on developing 100-Tb/s-plus in-package silicon photonic interfaces. Ayar’s TeraPHY chiplet combines silicon photonics and CMOS in a flip-chip SiP. Thermal ...
Electronics Weekly

IBM beats finFETs with vertical CMOS at IEDM

IBM revealed vertical FET CMOS logic at a sub-45nm gate pitch on bulk silicon wafers at the IEEE International electron devices meeting in San Francisco this week. IBM’s VTFET with a vertical channel ...